Electronic computing circuits



United States PatentO ELECTRONIG COMPUTING CIRCUITS Geolfifey C.Tootill, 'Slirivenham,..England,sassignor to Nat onal:ResearchsDevelopment Corporatiom: London, England, a Britishcorporation Applicationvla'nualty 3,"1950,' Serial No. 136,441

Claims priority; application Gr-eat Britain Januaryi17, 1949 The presentinvention re1atesr-to-:ele'ctronic circuits forbinary-digitalcomputationandmore particularly to such circuit. arrangementsf'fonperforming ;the process of addition of twoa-binary; digital-numbers inthe-:series mode, :i. e.v binary numbers; each. of whichds'!representable=in.the='dynamic form as atemporalflseries 50felectricallsigna'ls.

Addition .is. the fundamental. arithmetical operation indig'i'taifcomputa'tidn. as. itcan .be shown :that. all other.

. 'arithmetic'aLwork-can be reduced tosimple addition and subtractionoperations; and that subtraction, in its turn, can be treated asaddition by theuseof complementary numbers. In-thezprocess of-additionoftwo'binary'digital numbers, 'A*=and-'B,-' in the series"'mode,'thenumbers to be adcled are considered "digit .by digit; beginning "withthe-least significant digitsyand-a :separa'te operation is performedinvolving each pair .of corresponding ,digits. During -the addition thenth di'g'itlof the'sum 'isdependent onnot' only' the"'nthfdigitsof. thenumbers Aiand B but also upon '.the "less" significant digits ofthenumbers. The eife'ct' of these' less.'.signifiant'digits may berepresented bythe digitof a thirdnumber madelupzof the carried unitswhich are'produ'ce'd :in the course "of the series of operationscomprising .the .process -of addition. At each 'st'ep -of= thedd'ition*process therefore, his I necessary to I take "the' corresponding digitsA-- and B o'f-the two numbers-A "and Band 'alsothe -'carry-'-dig'it?CDderlvedfrom the preceding-step and to.dete'rmine-from these threedigits whether the corresponding 1 digit in the answernumberA-+B'is-*a"0"" or a 1 -andal'sowhether or not there is'-aa1 digit C tobemultiplied by'2, i. e. carried forward, to become-the digit cn -for the'next stop of the process.

The table indicates the significancesof the digitin the sir-m A+Band-"of the'idigit C'sfor the eightipossible com- 0," 1, 2 and B'fort-h'e numbenof' 1 digits in'the groups A B;-.CD ':corresponds to :aunique combination of. the resultr'digitsz A i B a1id!:O.- (in systemsof'this type a -drgitrl is?represented'abyw-ai pulse and adig it '0 bythe absence/of apnlse.)v

Tzible Oombination- 1A. a? 01 A+B+oD'-A+B- 0 One known method :ofperforming thewprocess-of additionwof binary-digital. numbers. .reliesupon the fact that the digits of the input numbersA, B and Cmv affectthe answer. equally and that therefore theappropriatesig-.

nificancesfor the answer digitsA-i-Band may-zbeobtained-bydetermining,.by a count-ingaprocess, how many 'of the digits A,B'andl'Cn' are ls.?- Thecounting may be 'p'erfo-rmed'by a-digit-alprocess, which implies that the pulses representative ofthe digitsa'rearranged tobe non- 2,693,907 Patented Nov. 9, 195 4 2 coincident intimeor. may be-performedby an analogue method. Adding circuit arrangementsof the=type'described in patent application Serial No. 141,176, filedJanuary 30, .l 0,-.F. C. Williams et'al. and SeriaLNo. 105,352, filedJuly 18, 1949; F. C. Williams et a1., operateby the analogue-countingmethod; In the analogue type of counter the A, B, and-CD. pulses arearranged tooccur simultaneously at. a standard: leveland are added inamplitude;- the numberaof ls beingdeter- ICC ruined by observation oftheamplitudeofthe .combined signal. This method of countingenables-allthree input signalstobe consideredtatthe sametimeandtheoutput. (A-+B- and C) signals. to..beproduceddmmediately(apartv from the natural delaycaused by circuit time .constants).Anadding circuit based upon the-analogue countingmethod however requirescircuits whichare critically adjusted to produceamplitudestabilized-pulses and to=effect the: necessaryamplitudediscriminationfor the counting operation.

It: is the object of .thepresen-tvinvention to\provideabinary-digital-adding circuit of the type-referred to; which isadapted'to operate. with .numbers,.-.the corresponding digits of whichoccur simultaneously-, butWhich'does not require the maintenance of thecritical' circuit operating conditions necessary for the :successfuloperation ofadding circuits operation by .theanalogue counting method.

It isa further object of the-.inventiomto provide-an addingcircuit ofthe type referred Ito which functions by performing a sequence oflogical. i operations. between digital pulses; in such I aafa'shionthat. the requirements for thezproduction of desiredanswer digitsA+B=and C, corresponding toinput'digits .A, .B-and CD-are obeyedr' It isa further object -of .-the-.inventionwto provide a binary-digital-circuit-which is built up only; of'circuits arranged to perform thelogical-operations:correspondingto the logical 1 concepts. of AND, ORand =NOT as defined below.

Logical operations-are the simplest kindof operations which can becarried out on:numbers,-'and are those'operation's in? which the nthdigit: in theresulting: number depends only on the nth. (coincident)digit=or digits of the numbers operated upon. Thesimplest*positive'logical operation which can be -performed=on-a single'binary digital number =isto-change the :significance-of-eachdigit, i.e. .toreplace each 1" by-0 and vice versa';

This operation corresponds to the logical'concept NOT, the-result v ofthe operation performedon anumber or 'single digit-A-is-referred to asNOT-A and-the device performing;.the operation:being'referredto as a.NOT "device or a negator.

Thevother two logical operations which are employed in-'the presentinvention are'those"correspondingto the logical concepts of AND. and OK.The AND device' is *in effect 'augatecircuit'which provides 'anout- 1put digit of one significance when correspondirig digitsoflikesignificance"occurrrsimultaneously in eachone' of several appliedpulse :trains 'representativeof binary-digitalnumbers. The- ANDdevice'may be refe'rredto simplyasxa'gate' circuit. The OR device is abutter circuitwhich provides an output digit pulse. whenever a digitpulse common :at least" one "of La plurality of input circuits,interaction-between theinput circuits being eliminated by the nature ofthetbuffer circuit.

According to the present-invention there is=provided 1 a circuitarrangement-forproducing fromtwo :input'pulse trains-(A) and (B), eachrepresenting by its succession of pulses the-digits .ofa'binary numberand fed thereto onseparate lineszsimultaneously digit'by digit, a:finaloutput pulse train (A-l-R) :representing by' its succession of pulsesthe digits ofrthe binary-sum of the two numbers, the'said'circuitarrangement'comprising-a first gate circuitfedwith trains (A) and (B).to produce a carry-digitpulse (C) wheneverpulses representing the digitone occur simultaneously in trains (A)'and (B),

. a delay circuit fed with-and arranged to' delay by one digitvperiodsaid pulses-(C) vto producea third-input pulse train. (CD),-meansincluding a second gate circuit fed with train (CD) to produce a pulse(C) whenever a pulse in the=train (CD) :occurs simultaneously with apulse representing the. digit. .one in either of trains: (A)

or (B), a'negator device'fe'd with pu1ses..(C) fromsaid first and secondgate circuits to produce an output pulse whenever no pulse (C) isapplied thereto, a third gate circuit and a butler circuit each fed fromthe three input trains A, B and CD to produce respectively an outputpulse when pulses representing the digit one occur either simultaneouslyin all three trains or in any one of the trains, and a final outputcircuit, including a fourth gate circuit, fed from said negator device,a third gate circuit and a buffer circuit to produce said final outputpulse (A-l-B) whenever an output pulse from said butfer circuit occurssimultaneously with an output pulse from either said negator device orsaid third gate circuit.

According to the present invention there is also provided the method ofproducing from two input pulse trains (A) and (B), each representing byits succession of pulses the digits of a number, a final output pulsetrain (A +B) representing by its succession of pulses the digits of thebinary sum of the two numbers, by deriving a carry digit pulse (C) fromtrains (A) and (B) whenever pulses representing the digit one" occursimultaneously in trains (A) and (B), delaying said pulse C by one digitperiod to produce a third input pulse train (CD), deriving a pulse Cwhenever a pulse in the train (Co) occurs simultaneously with a pulserepresenting the digit one in either of trains (A) or (B), deriving afirst output pulse train by generating a pulse on each occurrence of nopulse C, deriving a second output pulse train by generating a pulse oneach simultaneous occurrence of a digit one in all three input pulsetrains (A), (B) and (CD), deriving a third output pulse train bygenerating a pulse on each occurrence of a digit one" in any one inputtrain and deriving a final output pulse train representing the sum (A+B) by generating a pulse on each simultaneous occurrence of a pulsefrom said third output pulse train with a pulse from either said firstor said second output pulse trains.

In the accompanying drawings:

Figure 1 illustrates a logical diagram of one embodiment of theinvention;

Figure 2 illustrates a further logical diagram of a second embodiment ofthe invention;

Figure 3 illustrates a circuit diagram of an adding circuit according tothe invention;

Figure 4 shows the waveforms associated with the operation of thenegator device (valve D1 of Figures 1 and 3).

In Figure 1 it will be seen that the binary digital pulse trains to beadded are fed simultaneously on separate lines digit by digit to an ANDgate ll, AND gate 2, OR gate 3, and OR gate 10. The inputs A and B fedto the AND gate 2 produce an output whenever a pulse representing adigit 1 is present in both input pulse trains A and B. Similarly a pulsewill be produced at the output of OR gate 3 whenever a pulserepresenting a digit 1 is present in either input pulse train A or inputpulse train B. The output of OR gate 3 is applied to AND" gate 4together with a carry-digit pulse which may be present as a result of aprevious operation. AND" gate 4 therefore produces an output wheneverthere is a pulse representing a digit 1 in either the A or B pulsetrains and also a pulse representing a digit 1 in the Co (carry-digit)pulse train. The output from AND gate 4 and AND gate 2 are both fed tothe OR gate 6 which produces an output whenever a pulse from either ANDgate 2 output or AND gate 4 output is present at its input. The outputpulse from the OR gate 6 is fed into a delay circuit which delays thepulse for one digit period and this delayed pulse is one pulse in thepulse train CD which is fed to the AND gate 4, the AND gate 1 and the ORgate 10. The output from OR gate 6 is also fed to a negator device whichproduces an output pulse whenever there is no pulse at its input. Anoutput pulse from the negator device therefore represents a case of NOTC where C is the output pulse from the OR gate 6.

AND gate 1 is fed with pulse trains A, B and CD and produces an outputwhenever a pulse representing a digit 1 occurs in all three input pulsetrains. The output from AND gate 1 is fed together with the output fromthe negator 7 to OR gate 8 which gate produces an output pulse whenevereither a pulse representing (A-|-B+C1J) or a pulse representing NOT C ispresent at its input.

The OR gate 10 is fed with the three input pulse trains A, B and CD andproduces an output pulse whenever a pulse representing a digit 1 ispresent in either A fed with the outputs from OR gate 8 and OR gate 10and produces an output pulse whenever a pulse representing digit 1 ispresent in the output of OR gate 10 and that of the output of OR gate 8(representing A or B or CD and NOT C or A-l-B-l-Cp). The output from theAND gate 9 represents by its succession of pulses the digits of thebinary sum of the two numbers represented by the pulse trains A and B.

An alternative embodiment of the invention is shown in Figure 2. In thisembodiment the pulse trains A and B are fed simultaneously digit bydigit on separate lines to the AND gate 1 and to the OR gate 2. The ANDgate 1 produces an output pulse whenever a pulse representing digit 1 ispresent in both input pulse trains. This output is applied to the inputof AND gate 4 and OR gate 5. A pulse representing a carry digit CD(produced from a previous step) is also applied to the AND gate 4 whichproduces an output whenever a pulse representing A-l-B and a pulserepresenting Co is present at its input. The OR gate 2 produces anoutput pulse whenever a pulse representing a digit 1 is present ineither of input trains A or B and this is applied together with the CDpulse to the AND gate 3. The output of the AND gate 3 representing A orB plus CD is applied together with the output of AND gate 1 to the ORgate 5 which produces a pulse C whenever a pulse representing A or B orCD is present at its input. This output pulse C is applied to a negatordevice 6 and a delay device 10. The negator device 6 produces a pulserepresenting NOT C whenever it has no pulse at its input and this pulserepresenting NOT C is applied to the AND gate 9. The delay device 10produces the carry-digit pulse CD referred to above. The OR gate 8 isfed with the carry-digit pulse and the output from the OR gate 2representing A or B. OR gate 8 therefore produces an output pulsewhenever A or B or CD is present at its input and this output pulse isapplied together with the NOT C pulse to AND gate 9 which produces anoutput whenever the NOT C pulse and A and B or Co is present at itsinput. The output pulse from AND gate 9 is applied together with theoutput pulse from AND gate 4 to the OR gate 7 which produces an outputwhenever it has one input pulse only. The output of the OR gate 7 by itssuccession of pulses the digits of the binary sum of the two numbersrepresented by the two input pulse trains A and B.

Figure 3 illustrates the circuit diagram of the adding circuit. Thevarious input terminals of the circuit are indicated by the referencesA, B, CD corresponding to the digit pulses A, B of the numbers A and Bto be added and the carry digit pulse CD, derived from the precedingstep of addition, which are fed to these terminals. The pulsesrepresenting digits of significance l are arranged to be negative-goingwith a peak potential of l5 volts while the resting level of the pulsewave corresponding to digits of significance 0 is a potential of +5volts. The adding circuit comprises two main portions; a first partconsisting of two gates or AND devices and two buffers or OR devices,which derives from the digit pulses A and B and the carried digit pulseCD the pulse representative of the digit C to be carried, and a secondpart coupled to the first part by a NOT device or negator, andcomprising two OR devices and two AND devices, which generates the sumor answer digit pulse A+B.

In the first portion of the adder circuit the first OR device consistsof the diodes D1 and D2, to the cathodes of which are fed the A and Bpulses While the anodes of the diodes are connected in parallel andthrough resistor R1 to a source of positive potential (+200 volts). Thefirst AND device comprises the two-diode gate D3, D4, the anode of D4being fed with the carry-digit pulse C while the anode D3 is fed withthe output potential at point a from the first OR device. The commoncathode connection of D3 and D4 is connected to a source of negativepotential (200 volts) through resistor R2, the output being obtained atpoint b. The second AND device comprises the diodes D5, D6 to the anodesof which are fed A and B pulses, the common cathode output point 0 beingreturned to the negative potential source via resistor R3. The second ORdevice comprises the diodes D7, D3, the cathodes of which are fed withthe potentials at the output points b and c of the preceding pulses (A),(B) and (CD) to produce at its output a pulse representing the digit onewhenever a pulse occurs simultaneously in the (A), (B) and CD) trains,at third buffer circuit including at least one thermionic valve with itsinput connected to the outputs of said negator device and said thirdcoincidence gate circuit, a fourth buffer circuit including at least onethermionic valve to the input of which are applied the pulse trains (A),(B) and (CD), a fourth coincidence gate circuit, circuit meansconnecting the output of said third buffer circuit to one input of saidfourth coincidence gate circuit, circuit means connecting the output ofsaid fourth buffer circuit to the other input of said fourth coincidencegate circuit, and an output line for said (A-i-B) train connected to theoutput of said fourth coincidence gate circuit.

2. A circuit arrangement for producing from two input trains (A) and(B), each representing by its succession of pulses the digits of abinary number and fed thereto on separate input lines simultaneouslydigit by digit, a final output pulse train (A-I-B) representing by itssuccession of pulses the digits of the binary sum of the two numbers,said circuit arrangement comprising a first coincidence gate circuit fedwith trains (A) and (B) to produce at its output a pulse representingthe digit one whenever pulses representing the digit one occursimultaneously in trains (A) and (B), a first buffer circuit includingat least one thermionic tube with its input connected to both the (A)and (B) input lines, a second coincidence gatecircuit, circuit meansconnecting the output of said first butter circuit to one input of saidsecond coincidence gate circuit, a second butter circuit including atleast one thermionic tube. circuit means connecting the input of saidsecond buifer circuit to the outputs of said first and secondcoincidence gate circuits, a delay circuit connected to the output ofsaid second buffer circuit to delay by one digit period the pulses (C)derived from said second buffer circuit, means for applying the delayedpulses (Cu) to the other input of said second coincidence gate circuit,a negator device forproducing an output pulse representing the digit onein the absence of an input pulse at any digit position of said pulsetrains, circuit means connecting the output of said second buffercircuit to the input of said negator device, a third buffer circuitincluding at least one thermionic tube having an input to which areapplied the pulses (CD) and the output of said first butter circuit, athird coincidence gate circuit, circuit means connecting the output ofsaid negator device to one input of said third coincidence gate circuit,circuit means connecting the output of said third buffer circuit to theother input of said third coincidence gate circuit, a fourth coincidencegate circuit to one input of which is applied the output of said firstcoincidence gate and to another input of which is applied said pulses(CD) a fourth buffer circuit including at least one thermionic valve tothe input of which are applied the outputs of said third and fourthcoincidence gate circuits, and an output line for said (A-t-B) trainconnected to the output of said fourth buffer circuit.

3. A circuit arrangement for producing from two input pulse trains (A)and (B), each representing by its succession of pulses the digits of abinary number and fed thereto on separate input lines simultaneouslydigit by digit, a final output pulse train (A +B) representing by itssuccession of pulses the digits of the binary sum of the two numbers,said circuit arrangement comprising a first double diode AND type gatecircuit having two input terminals fed respectively with said trains (A)and (B) and an output terminal, a first double diode OR type gatecircuit having two input terminals supplied respectively with saidtrains (A) and (B) and an output terminal, a second double diode ANDtype gate circuit having two input terminals and an output terminal, oneof said input terminals of said second AND type gate circuit beingconnected to the output terminal of said first OR type gate circuit, asecond double diode OR type gate circuit having two input terminals andan output terminal, one of said input terminals of said second OR typegate circuit being connected to the output terminal of said first ANDgate type circuit and the other of said input terminals being connectedto the output terminal of said second AND type gate circuit, a negatordevice having input and output terminals and producing an output signalrepresenting .the digit 1 during each digit interval period of the inputpulse trains in the absence of an input pulse to its input terminalduring such interval, a delay device having input and output terminalsfor delaying pulses applied thereto by a time interval equal to onedigit interval period of the input pulse trains, circuit meansconnecting the output of said second OR type gate circuit to said inputterminal of said negator device and to the input terminal of said delaydevice to provide a series of delayed pulses (CD), a triple diode ANDtype gate circuit having three input terminals supplied respectivelywith said trains (A), (B) and (CD) and an output terminal, a thirddouble diode OR type gate circuit having two input terminals and anoutput terminal, said input terminals of said third OR type gate circuitbeing connected respectively to the output terminal of said negatordevice and the output terminal of said triple diode AND type gatecircuit, a triple diode OR type gate circuit having three inputterminals and an output terminal, said input terminals being suppliedrespectively with said (A), (B) and (Co) pulse trains, a fourth doublediode AND type gate circuit having two input terminals and an outputterminal, said input terminals of said fourth AND type gate circuitbeing connected respectively to the output terminal of said triple diodeOR type gate circuit and the output terminal of said third OR type gatecircuit and a sumrepresenting signal output terminal connected to theoutput terminal of said fourth AND type gate circuit.

4. A circuit arrangement for producing from two input pulse trains (A)and (B) each representing by its succession of pulses the digits of abinary number and fed thereto on separate input lines simultaneouslydigit by digit a final output pulse train (A-l-B) representing by itssuccession of pulses the digits of the binary sum of the two numbers,said circuit arrangement comprising a first double diode AND type gatecircuit having two input terminals fed respectively with said trains (A)and (B) and an output terminal, a first double diode OR type gatecircuit having two input terminals supplied respectively with saidtrains (A) and (B) and an output terminal, a second double diode ANDtype gate circuit having two input terminals and an output terminal, oneof said input terminals of said second AND type gate circuit beingconnected to the output terminal of said first OR type gate circuit andthe other of said input terminals being supplied with a pulse signal(Co) comprising carry-over digit signals from the immediately precedingaddition operation, a second double diode OR type gate circuit havingtwo input terminals and an output terminal, one of said input terminalsof said second OR type gate circuit being connected to the outputterminal of said first AND type gate circuit and the other of said inputterminals being connected to the output terminal of said second AND typegate circuit, a negator device having an input and an output terminaland producing an output signal representing the digit 1 during eachdigit interval period of the input pulse trains in the absence of aninput pulse to its input terminal during each such interval, circuitmeans connecting the output of said second OR type gate circuit to saidinput terminal of said negator device, a triple diode AND type gatecircuit having three input terminals supplied respectively with saidpulse trains (A), (B) and (CD), a third double diode type OR gatecircuit having two input terminals and an output terminal, said inputterminals of said third OR type gate circuit being connectedrespectively to the output terminal of said negator v device and theoutput terminal of said triple diode AND type gate circuit, a triplediode OR type gate circuit having three input terminals and an outputterminal, said input terminals of said triple diode OR type gate circuitbeing supplied respectively with said (A), (B) and (CD) pulse trains, afourth double diode AND type gate circuit having two input terminals andan output terminal, said input terminals of said fourth AND type gatecircuit being connected respectively to the output terminal of saidtriple diode OR type gate circuit and the output terminal of said thirdOR type gate circuit and a sum-representing signal output terminalconnected to the output terminal of said fourth AND type gate circuit.

5. A circuit arrangement for producing from two input pulse trains (A)and (B), each representing by its succession of pulses the digits of abinary number and fed thereto on separate input lines simultaneouslydigit by digit,

a final outputpulsextrain (A -1+1?)representingbyits1suc=:.

cession :ofupulses :the digitsof the" .binarysum-bf: the two.

numbers; said; circuit arrangement icomprising; a first doubleadiode'zAND type =gate. circuit. having; two input :terminals fed respectivelywith said trains (A) and (B) and an; output terminal,-afirstidoubleidiode OR type gatecircuit havingntwo input terminals:suppliedrespectively with.said trains-(A). and-(B); andran outputterminal, a second double diode :AND type gate: circuit having. twoinput .terminals and:anioutputzterminal, one of .saidrinputv terminalsbeinglconneotedztov theaoutputt terminal of said. fiISlZJOR type:gateucircuitxandthegother ofsaid-input terminals beingsuppliedwith apulse-signal .train (CD) comprising. carryeover digit: signals :from:the immediately precedingaddition opera'tiomza second double diode ORtypegate circuit havingtwo input terminals and.:an outputterminal, oneof said input terminals being connected to the output terminal of; said;firstw-AND ttypegate circuit and .thBiOthGlfOf said :inputterminalstbeingiconnected to theroutput terminal of isaid second ANDtype gate=circuit, a negatordevicewhaving; an input terminal and anoutput. terminal and producing-:an.;output signal; representingthe;digitp1 duringeach digitrinterval period of the input pulse'trainsin the absence of an input pulse to itsinput terminal duringeach such.interval, a delay device having inputand. output terminals for delayingpulses applied thereto'by a time interval equal to one digit intervalperiod of the'input pulsetrains; circuit means connectingthe'outputterminal of saidsecond OR type gate circuit to said input. terminal ofsaid negator devicezandrto the input terminal of saiddelay devicetorprovidetsaid-carry-over' pulse train (CD), at the :outputterminal:.of:saidi delay device, a third doublediodezOR-type-gate.ciruit havingtwo input terminals connectedrespectively to the output I terminals of said first OR type gatecircuit and said output terminal of said delay device and anoutput-terminal, a thirdrdoublediode ANDtype gate circuit having twoinput-terminals connected respectively to the output ter-' minal of saidnegator device and the-output terminal of said third OR type gatecircuit, a fourth double diode AND type gate circuit having two inputterminals connected respectively to the output terminal of said firstAND type gate circuit and-the output terminal of said delay.- device, afourth double-diode OR type gate circuit having two inputterminals-connected respectively to the outputaterminal of said fourthANDtype gate circuit and theoutput terminal of said third AND type gatecircuit and :a sum-representing signal'output terminal connected to theoutput terminal of said fourth OR type gate circuit. 6. A circuitarrangement for producing-from two input pulseqtrains (A) and (B), eachrepresenting by its succession-ofi pulses the digits of a binary numberand fed'thereto on separate inputlines simultaneously digit by digit, a1 finaltoutput pulse train (A-l-B) representing by its suc-. cession' ofpulses thedigits of the binary sum of the two numbers, saidlcircuitarrangement comprising a first double diode AND type gate circuit havingtwo' input terminals fed-respectively with said trains :(A) and (B) :andan output terminal, a first double diode-OR type gate circuit having twoinput terminals .suppliedrespectively with said trains (A) and (B) andanoutput terminal, a second double diode AND type gate circuit having twoinput terminals and an output terminal, one'of saidinput terminals beingconnected to the output terminal-of SaId'fiI'St OR type gate circuit andthe'other of said input terminals being supplied with a pulse signaltrain (CD) comprising carry-over digit signals from the preceding addingoperation,;a second double diode'OR type gate circuit having;

two input terminals and an output terminal, one of saidinput-terminals-being connected to the output. terminal ofsaid first ANDtype gate-circuit and the other.v of said input terminals beingconnected to the output terminal of said second AND type gate circuit, anegator device having ,an input terminal and an output terminal andpro-vducing an output signal representing-the-digit "1 during each digitinterval period of the input pulse trains in the absence of an inputpulse to its input terminal during each' such interval, circuit meansconnecting the'output terminal of said second.- OR type gatecircuit tosaid input ter-r minal. of said :negator device, :athird double diodeOR.

type gate circuit having two input terminals and an output terminal,.oneof said'input terminals beingconnected to thetoutput' terminal ofsaid'first OR type gate-circuit and the-other of said input terminalsbeing supplied with. said pulse train: (CD), .a third double diodezAND.typegatecir-sv cuitzhavingi two. input; terminals 1' and:iamtoutputiterminalg a saidninput vzterminals; being.connectedzt-respeetively': tonthel output. terminal of. saidnegatomdeviice andith'e' output tere minal of said third OR-ttype' gate;circuitti a1 fiounthiidouble' diodevAND .typew gate circuitahaving twoinput-terminals and .a'n output terminal, oneiof :said inputterminalstbeing connected; to: the .output. terminal .ofi-saidfirstuAND)type-w gate' -circuitnand, :the other.inpututerminallbeing supplied: awith said; (C11) pulsertrain, a.fourthrdoubletdiodeOR typesgatescircuitihavi gitwo input terminals andx-anoutput tern minal, said!input terminals; being:connectedxrespectively 1 to'..the. output".terminal; 0f.T:JS3,idlifOll1lIh'=. AND type; gate circuitzandi theoutput.terminalsofnsaid thirdwAND type. gate circuit and a sum-representingsignal output terminals; connected, to: the outputv .terminaltof; said.fourth: OR type gate tcircuit-.:.

7. A circuit arrangement..forneflecting:binarya addition-t; of twonumbers reachvrepresented: ;by.rserialapulsestrains (A) and, (B )1wherein ibinary. digit; value :1 t is 'signalledc: byrthepresence .ofapulseiimany oft a number;0f: successive. digit. interval times.:andrwhereinrthe:binary: value 0 is t. signalled-aby thea absencei ofijapulseaduringzsuch. .digitc interval .timesand whichwomprises first andsecond input: terminalsfor receivingmespectively said input=.pulsetrainsra. (A) andw(B) and athirdterminal;receiving.axtrainnoftz:delayed-carry pulses; (C11)..- derived during; the. preceding: additionoperation; a .threeeinputnAND gate having its inputs connected.-respectively; to saidv -.first, .second i. and: thirditerminals,..athree-inputORgate having itsinputs connected; respectively: to.saidwfirst second; and; third tere minals, afirst two-inputzAND'zgatehaving itstinputx ter-H minals; connectedurespectively. .to said; firstand second. inputterminals a first two-inputcOR- gate havingtits'input;terminals connected .-to said: first and; second input. termi-L rnals,i.-a vsecondntwo-input AND gate havingone of. its input terminalsconnected towtheioutput :of said first two-. input OR' gate: and havingthe other; of. its input. .terminals connected toisaidnthird terminal -21.second two-input; OR gateihavingoneiofit's inputsrconnected; tothe'outputt. of said; first two-input. AND gate. andthe: other of its.inputs connected to- -the-output-10f.said;:second:ttwo-input AND gate, adelay. device imposingia delayzequalto enemof-said digit1intervalvtimeuperiodsaof said .pulse trainsizt andhavingaits'inputconnectedaoithe output ofisaidtsecond, two-input .ORgateand ..having-, its output. connected-ton. said=-third terminal,; anegator :device; producing an: output-s; pulserepresentative ofv digitin each .digit. interval in, thetabsencenofanz appliedeinput pulsethereto; during thatv interval, said negator devicehavingits inputconnected: to the. output of said second two-input ORgate, :a third- 1',two input: :OR .gatethaving one 10f its-.inputsiconnected to theoutput-of. saidrsnegator' devicexan'dwthe [other of its inputsiconnected totheIoutputaof said three-input AND gate, a third two-inputAND- gate having one of its inputs connected to theoutput ofsaidthree-input OR gate-and the other of.its inputsconnectedtonthetzoutputr=of said; third two-input ORhgate-zarrdasumrrepresentin'g signal output: terminalv connected to the output. ofsaid third .twtrinput -AND gate.

8. Acircuit arrangement for't effectingtbinary addition of. two numberseach *represented' by serial; pulse trains (A) and-(B) wherein binary.digitwalue. -.-l is signalled by 'the presence. of-a pulse; inhanyuoflanumber of successive digit interval times-andtwhereimthezbinary value-M0 is asignalled. vby the absence of .a pulse I during such dig'it'intervaltimes. andvwhich comprises! firstz and' second input terminalsforreceiving respectively-said input pulse trainsq-(A). and t (B): and-a third terminalueceiving :a trainof-delayedacarry pulses-J (CD)derived during the precedingzgaddit-ion operation ra .threeainputw ANDgate having its inputs connected respectively .tosaid. first,--f= secondand third-terminals, a (three-input 0R .-gate.-hav- .ing', its inputsconnectedsrespectively. to said :first, secondand; third terminals, afirst: two-input 'AND gatezhavingr. 0 its input-terminals. connectedrespectively to vsaid-first Y and second input terminals-,aavfirstwtwo-i nput20R :gate having. its input terminals: connected to 1said .lfiI'St' sands";- secondt input terminals,- a second two-input ANDgate :2 havingtone of its input terminals connected -.to=the out:-=.:'

put. of said-first two-input; OR: gate -andwhaving the r to the:

device producing an output pulse representative of digit 1 in each digitinterval in the absence of an applied input pulse thereto during thatinterval, said negator device having its input connected to the outputof said second two-input OR gate, a third two-input OR gate havlng oneof its inputs connected to the output of said negator device and theother of its inputs connected to the output of said three-input ANDgate, a third twoinput AND gate having one of its inputs connected tothe output of said three-input OR gate and the other of its inputsconnected to the output of said third twoinput OR gate and asum-representing signal output terminal connected to the output of saidthird two-input AND gate.

9. A circuit arrangement for effecting binary addition of two numberseach represented by serial pulse trains (A) and (B) wherein binary digitvalue 1 is signalled by the presence of a pulse in any of a number ofsuccessive digit interval times and wherein the binary value issignalled by the absence of a pulse during such digit interval times andwhich comprises first and second terminals for receiving respectivelythe input pulse trains (A) and (B), a third terminal receiving a trainof delayed carry pulses (CD) derived within the circuit arrangement, afirst two-input AND gate having its inputs connected respectively tosaid first and second terminals, a first two-input OR gate having itsinputs connected respectively to said first and second terminals, asecond two-input AND gate having one of its inputs connected to theoutput of said first two-input OR gate and the other of its inputsconnected to said third terminal, a second two-input OR gate having oneof its inputs connected to the output of said first two-input AND gateand the other of its inputs connected to the output of said secondtwo-input AND gate, a delay device imposing a time delay upon signalsapplied thereto equal to one digit interval time of said pulse trains,said delay device having its input connected to the output of saidsecond two-input OR gate and having its output connected to said thirdterminal, a negator device producing an output pulse representing digitvalue 1 in any digit interval time in the absence of an input pulseapplied thereto during that same interval time, said negator devicehaving its input connected to the output of said second two-input ORgate, a third two-input OR gate having one of its inputs connected tothe output of said first two-input OR gate and the other of its inputsconnected to said third terminal, a third two-input AND gate having oneof its inputs connected to the output from said negator device and theother of its inputs 7 connected to the output from said third two-inputOR gate, a fourth two-input AND gate having one of its inputs connectedto the output of said first two-input AND gate and the other of itsinputs connected to said third terminal, a fourth two-input OR gatehaving one of its inputs connected to the output of said fourth twoinputAND gate circuit and the other of its inputs connected to the output ofsaid third two-input AND gate and a sum-representing signal outputterminal connected to the output of said fourth two-input OR gate.

10. A circuit arrangement for effecting binary addition of two numberseach represented by serial pulse trains (A) and (B) wherein binary digitvalue 1 is signalled by the presence of a pulse in any of a number ofsuccessive digit interval times and wherein the binary value 0 issignalled by the absence of a pulse during such digit interval times andwhich comprises first and second terminals for receiving respectivelythe input pulse trains (A) and (B), a third terminal receiving a trainof delayed carry pulses (CD) derived within the circuit arrangement, afirst two-input AND gate having its inputs connected respectively tosaid first and second terminals, a first two-input OR gate having itsinputs connected respectively to said first and second terminals, asecond two-input AND gate having one of its inputs connected to theoutput of said first two-input OR gate and the other of its inputsconnected to said third terminal, a second two-input OR gate having oneof its inputs connected to the output of said first two-input AND gateand the other of its inputs connected to the output of said secondtwo-input AND gate, a negator device producing an output pulserepresenting digit value 1 in any digit interval time in the absence ofan input pulse applied thereto during that same interval time, saidnegator device havingits input connected to the output of said secondtwo-input OR gate, a third twoinput OR gate having one of its inputsconnected to the output of said first two-input OR gate and the other ofits inputs connected to said third terminal, a third twoinput AND gatehaving one of its inputs connected to the output from said negatordevice and the other of its inputs connected to the output from saidthird twoinput OR gate, a fourth two-input AND gate having one of itsinputs connected to the output of said first two-input AND gate and theother of its inputs connected to said third terminal, a fourth two-inputOR gate having one of its inputs connected to the output of said fourthtwo-input AND gate circuit and the other of its inputs connected to theoutput of said third two-input AND gate and a sum-representing signaloutput terminal connected to the output of said fourth two-input ORgate.

11. A circuit arrangement according to claim 3 wherein said pulse trains(A), (B) and (Co) comprise negative-going pulses for signalling thebinary digit value 1 and wherein each of the diodes in each of said ANDtype gate circuits has its anode connected to the related input terminaland its cathode directly connected to said output terminal of said gatecircuit, there being also a source of negative potential and a loadresistor connected between said output terminal and said source ofnegative potential, and wherein also each of the diodes in each of saidOR type gate circuits has its cathode connected to the related inputterminal and its anode directly connected to said output terminal ofsaid gate circuit, there being also for each gate circuit a source ofpositive potential and a load resistor connected between said outputterminal and said source of positive potential.

12. A circuit arrangement according to claim 5 wherein said pulse trains(A), (B) and (CD) comprise negativegoing pulses for signalling thebinary digit value 1 and wherein each of the diodes in each of said ANDtype gate circuits has its anode connected to the related input terminaland its cathode directly connected to said output terminal of said gatecircuit, there being also a source of negative potential and a loadresistor connected between said output terminal and said source ofnegative potential, and wherein also each of the diodes in each of saidOR type gate circuits has its cathode connected to the related inputterminal and its anode directly connected to said output terminal ofsaid gate circuit, there being also for each gate circuit a source ofpositive potential and a load resistor connected between said outputterminal and said source of positive potential.

13. A circuit arrangement according to claim 7 wherein said pulse trains(A), (B) and (CD) comprise negative-going pulses for signalling thebinary digit value 1 and wherein each of said AND gates comprises aplurality of unilaterally conductive devices, one for each input, theanode forming terminal of each device being connected to the associatedinput and the cathode forming terminals of all the devices beinginterconnected to form an output terminal, a source of negativepotential, and a load resistor connected between said output terminaland said source of negative potential, and wherein each of said OR gatescomprises a plurality of unilaterally conductive devices, one for eachinput, the cathode forming terminal of each device being connected tothe associated input and the anode forming terminals of all the devicesbeing interconnected to form an output terminal, a source of positivepotential and a load resistor connected between said output terminal andsaid source of positive potential.

14. A circuit arrangement according to claim 9 wherein said pulse trains(A), (B) and (CD) comprise negativegoing pulses for signalling thebinary digit value 1 and wherein each of said AND gates comprises aplurality of unilaterally conductive devices, one for each input, theanode forming terminal of each device being connected to the associatedinput and the cathode forming terminals of all the devices beinginterconnected to form an output terminal, a source of negativepotential, and a load resistor connected between said output terminaland said source of negative potential, and wherein each of said OR gatescomprises a plurality of unilaterally conductive devices, one for eachinput, the cathode forming terminal of each device being connected tothe associated input and the anode forming terminals of all the devicesbeing interconnected to form an output terminal, a source of positivepotential and a load resistor connected between said output terminal andsaid source of positive potential.

References Cited in the file of this patent UNITED STATES PATENTS NumberOTHER REFERENCES First Draft of a Report on the EDVAC, John Von Neuman,Moore School of Electrical Engineering, Uni- 5 versity of Pennsylvania,June 30, 1945; pages 24-29 (May Name Date Progress Report (2) ontheEDVAC, Moore School Ra-chman July 16 1946 of Electrical Engineermg,University of Pa., June 30, snglder Aug. 1947 1946, declassifiedFebruary 13, 1947; Fig. 13-1 on page Herbst Oct. 21, 1947 10 1 114A-Herbst Oct. 21, 1947 Flory July 13, 1948

